1. Field of the Invention
The present invention relates to a semiconductor memory device and data read method thereof capable of performing a 2 cycle pipelined operation without errors.
2. Description of the Prior Art
A synchronous type semiconductor memory device performs read and write operations responsive to an external clock signal. One disadvantage to this type of device is the amount of time it takes for the semiconductor memory device to respond to a read address and transmit the read data stored in the cell to a data output buffer through a bit line pair, a data line pair, and a sense amplifier. Therefore, if the frequency of the clock signal becomes shorter than the time for the read data to be transmitted to the data output buffer, the read data will not be output to the external device.
The pipeline method of reading data was designed to solve this problem. The pipelined method responds to the read command and outputs the read data transmitted from a memory cell to the data output buffer out to the external device after one cycle of the read command. However, the operational advantages of using the conventional pipelined read method are limited as semiconductor memory devices operate at high frequencies.
The present invention presents a method for performing a 2 cycles read latency operation where the conventional pipelined method is considered as a 1 cycle read latency operation. In other words, the 2 cycles pipelined method of the present invention responds to the read command and outputs the read data transmitted from the memory cell to the data output buffer out to the external device after 2 cycles of the read command. One question is whether this method can be performed without errors using a conventional data output buffer. In result, if the clock signal has a high frequency, the conventional data output buffer can perform the 2 cycles pipelined operation. If the frequency of the clock signal is low, it cannot perform the 2 cycles pipelined operation.
FIG. 1 is a block diagram of a data read method for a conventional semiconductor memory device. The device is comprised of memory cells 10-1, 10-2, . . . , 10-n, free charging and equalizing circuits 12-1, 12-2, . . . , 12-n, a row address decoder 14, column selecting switches 16-1, 16-2, . . . , 16-n, a column address decoder 18, a sense amplifier 20, and a data output buffer 22.
The memory cells 10-1, 10-2, . . . , 10-n are selected by a word line selection signal. The free charging and equalizing circuits 12-1, 12-2, . . . , 12-n free-charge and equalize bit line pairs BL1 and BLB 1, BL2 and BLB2, . . . , Bln and BLBn during the execution of the read operation. The row address decoder 14 decodes a row address X and generates word line selection signals WL1, WL2, . . . , WLn. The column address decoder 18 decodes a column address Y and generates column selection signals Y1, Y2, . . . , Yn. The column selection switches 16-1, 16-2, . . . , 16-n respectively respond to the column selection signals Y1, Y2, . . . , Yn and transmit the data from the selected bit line pair to the pertinent data line pairs DLk and DLBk. The sense amplifier 20 is enabled during the execution of the read command, detects and amplifies the difference in data transmitted to the data line pair DLk and DLBk, and generates the sense output signal pair SASk and SASBk. The data output buffer 22 is input to the sense output signal pair SASk and SASBk, buffers it and generates data output signal pair DOUk and DODk.
FIG. 2 is a block diagram of the data output buffer 22 shown in FIG. 1. The data output buffer 22 comprises a level shifter 30, register 32, an inverter 34, a latch 36, and logical multiplication means 38. The level shifter 30 receives the sense output signal pair SAS and SASB, shifts their level and generates data output signal pair DA and DAB. The register 32 generates the data output signal pair DB and DBB by the data output signal pair DA and DAB. The inverter 34 inverts the data signal pair DB and DBB responsive to a signal KDATAIN and outputs it as data output signal pair DC and DCB. The latch 36 latches the data output signal pair DC and DCB. The logical multiplication means 38 outputs the data output signal pair DC and DCB as data output signal pair DOU and DOD responsive to an output enable control signal OE.
FIG. 3a is a circuit of the data output buffer 22 shown in FIGS. 1 and 2. The level shifter 30 is comprised of PMOS transistors P1, P2, and P3 and NMOS transistors N1, N2, N3, and N4. The register 32 is comprised of inverters II, I2, I3, and I4, PMOS transistors P4, P5, P6, and P7 and NMOS transistors N5 and N6. The inverter 34 is comprised of PMOS transistors P8, P9, P10, and P11 and NMOS transistors N7, N8, N9, and N10. The circuit for generating a data input control signal KDATAIN includes a NAND gate NAI and an inverter I3. The latch 36 is comprised of inverters I5 and I6. The logical multiplication means 38 is comprised of NAND gates NA2 and NA3 and inverters I3 and I5.
Once a read command is received, a control signal KDPRECB changes to a low level enabling the level shifter 30. The level shifter 30 detects the difference in voltage in the sense amplifier output signal pair SAS and SASB and outputs the data output signal pair DA and DAB. If the sense amplifier output signal SAS has a higher voltage than the reverse sense amplifier output signal SASB, the PMOS transistor P3 than the PMOS transistor P2. The data output signal DA changes to a high level and the inverse data output signal DAB changes to a low level. Alternatively, if the sense amplifier output signal SAS has a lower er voltage than the inverse sense amplifier output signal SASB, the data output signal DA changes to a low level and the inverse data output signal DAB changes to a high level.
The register 32 inverts the data output signal pair DA and DAB respectively by the inverters I2 and I1. If one single line of the data output signal pair DA and DAB is high and the other low, the output signal of the inverter I2 is at a low level and the output signal of the inverter I1 is at a high level. Then, the NMOS transistor N5 and the PMOS transistors P6 and P7 are turned on and the data output signal pair DBB and DB is respectively at a high and low level. On the other hand, if the data output signal pair DA and DAB is respectively low and high, the data output signal pair DBB and DB respectively changes to a high and low level. The data transmitted as the data output signal pair DBB and DB is stored in the latch I3 and I4. In other words, the register 32 transmits the data of the data output signal pair DA and DAB as the data output signal pair DBB and DB and latches it.
The inverter 34 is enabled responsive to a data output control signal KDATAIN resulting from the logical multiplication of a signal KDATA and READ1P. The signal KDATA is enabled by and synchronized with the clock signal every cycle. The signal READ1P is enabled after one cycle of the read command. In other words, when the data output control signal KDATAIN is at a low level, the PMOS transistors P9 and P11 and the NMOS transistors N7 and N9 are turned off, and the transmission of the data from the data output signal pair DBB and DB to the data output control signal pair DC and DCB is prevented. Alternatively, if the data output control signal KDATAIN is at a high level, the PMOS transistors P9 and P11 and the NMOS transistors N7 and N9 are turned on, respectively, inverting data from the data output signal pair DBB and DB and transmitting the data as the data output signal pair DC and DCB. The construction of the inverter 34 is that of a clocked CMOS inverter that inverts the data output signal pair DBB and DB and outputs it as the data output signal pair DC and DCB respectively. The latch 36 latches the data of the data output signal pair DC and DCB. The logical multiplication means 38 outputs the data output signal pair DC and DCB as the data output signal pair DOU and DOD responsive to the data output enable signal OE.
The conventional data output buffer as described above reads data from the appropriate memory cell and latches the data in the latch of the register 32 responsive to the read command. The data in the latch of register 32 is enabled after 1 cycle responsive to the output control signal KDATAIN and is transmitted to the latch 36 through the inverter 34. The data is then provided to an external device (not shown) responsive to the data output enable signal OE. Therefore, execution of the 1 cycle pipelined operation is possible in the conventional data output buffer such as output buffer 22.
FIG. 3b is a circuit diagram of the control signal generating circuit for enabling the sense amplifier 20 and the data output buffer 22. The circuit is comprised of a NOR gate NR1, PMOS transistors P12, P13, and P14, NMOS transistors N11 and N12, and inverters I6, I7, I8, I9, I10, I11, I12, and I13. Once a read command is received, a sense amplifier control signal MSAENP is enabled by a high level pulse and the data output signal pair DA and DAB changes to a low level. The output signal of the NOR gate NR1 changes to a high level and the NMOS transistors N11 and N12 are all turned on providing a low level signal to the drain terminal of the NMOS transistor N11. The inverters I6-I11 delay the low level signal changing the data output buffer control signal KDPRECB to a low level. The inverters I6, I12, and I13 invert and delay the low level signal of low level changing the sense amplifier enable signal MSAEN to a high level. The sense amplifier is enabled responsive to a high level sense amplifier enable signal MSAEN. Referring to FIGS. 4a and 4b, a 2 cycles pipelined operation of the data output buffer shown in FIG. 3a responsive to a low and high frequency clock signal is described.
In the 2 cycles pipeline method, the data output buffer 22 shown in FIG. 3a is enabled by the control signal READ2P instead of by the control signal READ1P. The control signal READ1P is enabled after 1 cycle of the read command. In contrast, the control signal READ2P is enabled after 2 cycles of the read command. FIGS. 4a and 4b show the execution of the 2 cycles pipelined operation after the control signal READ2P is applied. FIG. 4a is a timing diagram of the 2 cycles pipelined operation of the data output buffer 22 shown in FIG. 3a where a frequency clock signal is applied.
In FIG. 4a, the cycle time of the clock signal is approximately 10ns. Of these, 5-6ns (this is almost a fixed amount of time) are used to read data after the read command is received. The control signal KDATA is enabled responsive to a clock signal XCK during the execution of the read command. The control signal READ2P is enabled 2 cycles after the read command, as described above. The control signal READ2P is enabled in the third cycle III because the read command is received at the first cycle I of the timing diagram shown in FIG. 4a. The data output control signal KDATAIN is generated when the control signals KDATA and READ2P are logically multiplied. The data output control signal KDATAIN is synchronized with the control signal KDATA from the third cycle III.
In the first cycle I, the read data D1 pertinent to the first read command is latched in the register 32 after 5-6ns (hereinafter a predetermined time). In the second cycle II, the read data D2 pertinent to the second read command is latched into the register 32 after the predetermined time. Therefore, the read data D1 that was previously latched in the register 32 in the first cycle I may be lost.
In the third cycle III, the read data D2 that is stored in the latch of the register 32 is latched in the latch 36 through the inverter 34 responsive to the data output control signal KDATAIN. The read data D2 is then provided to external circuitry (not shown) as data Q2 through the logical multiplication means 38 responsive to the output enable signal OE. The read data D3 corresponding to the third read command is latched into the register 32 after lapse of the predetermined time. Despite that the read data D1 is output as data Q1 in the third cycle, the read data D2 is output as data Q2 due to the loss of the read data D1. Therefore, the first cycle error continues to affect the read cycle, keeping the 2 cycles pipelined read operation from performing precisely. In other words, the conventional data output buffer cannot perform the 2 cycles pipelined operation where the clock signal has a frequency.
FIG. 4b is a timing diagram of the 2 cycles pipelined operation of the data output buffer 22 shown in FIG. 3a where a high frequency clock signal is applied. In FIG. 4b, the cycle time of the clock signal is approximately 3ns. Of these, 5-6ns (this is almost a fixed amount of time) are used to read data after the read command is received. This is a 5-6ns period will be referred to as a predetermined time. The control signals are generated in a similar manner as are described with reference to FIG. 4a.
In the first cycle I, the read data D1 corresponding to the first read command is read. In the second cycle II, the read data D2 corresponding to the second read command is read and the read data D1 is transferred into the data output buffer after the lapse of the predetermined time. In the third cycle III, the read data D3 corresponding to the third read command is read and the read data D1 is latched into register 32. The read data D1 is then latched into the latch 36 through the inverter 34 responsive to control signal KDATAIN. The latched data D1 is then provided to external circuitry (not shown) as data Q1 through the logical multiplication means 38 responsive to data output enable signal OE. Then, the read data D2 is inputted into the data output buffer after lapse of the predetermined time.
In the fourth cycle, the read data D4 pertinent to the fourth read command is read and the read data D2 is latched into the register 32. The read data D2 is provided to external circuitry (not shown) as data Q2 responsive to the control signal KDATAIN. Then, the read data D3 is inputted into the data output buffer after the predetermined time. In a continuous read cycle, the 2 cycles pipelined read operation is performed without errors. Thus, the conventional data output buffer is able to perform the 2 cycles pipelined operation when the clock signal has a high frequency.
Consequently, the conventional data output buffer is able to perform the 2 cycles pipelined operation properly when the clock signal has a high frequency. However, where a low frequency clock signal is used, the data output buffer can not perform the 2 cycles pipelined operation properly. Even though the 2 cycles pipelined operation is used primarily for enabling high frequency operation, the 2 cycles pipelined operation should function error free where a low frequency signal is applied. Therefore, the conventional data output buffer cannot be said to have the construction necessary for executing the 2 cycles pipelined operation.
FIG. 5 is a block diagram of an improved data output buffer. The improved data output buffer comprises a level shifter 40, a register 42, a transmission gate 44, latches 46 and 50, an inverter 48, and logical multiplication means 52. The improved data output buffer shown in FIG. 5 latches the data in the latch 46 after transmitting the data through transmission gate 44 responsive to the control signal KDATAIN1. The improved buffer circuit latches the data in the latch 50 after inverting it in inverter 48 responsive to the control signal KDATAIN2. The control signals KDATAIN1 and KDATAIN2 are enabled 1 and 2 cycles after the read command is received.
The construction and function of the level shifter 40, the register 42, the inverter 48, the latch 50, and the logical multiplication means 52 are similar to level shifter 30, register 32, inverter 34, latch 36, and logical multiplication means 38 explained before with reference to FIG. 2. The transmission gate 44 transmits the data output signal pair DBB and DB latched in the register 42 responsive to the data output control signal KDATAIN1. The latch 46 latches the data output signal pair DC and DCB transmitted through the transmission gate 44.
FIG. 6 is a detailed circuit diagram of the improved data output buffer shown in FIG. 5. The circuit is comprised of the level shifter 40, the register 42, the transmission gate 44, the latch 46, the inverter 48, the latch 50, and the logical multiplication means 52. As mentioned above, the construction and function of the level shifter 40, the register 42, the inverter 48, the latch 50, and the logical multiplication means 52 are the same as the level shifter 30, the register 32, the inverter 34, the latch 36, and the logical multiplication means 38 shown are the same as in FIG. 3. The transmission gate 44 is comprised of the transmission gates T1 and T2 and the latch 46 of the inverters I14 and I15.
The inverter 48 inverts the data output signal pair DCB and DC and transmits it as the data output signal pair DD and DDB responsive to the second data output control signal KDATAIN2. Thus, rather than the NAND gate NA1 and the inverter I3 logically multiplying the control signals KDATA and READ1P and generating the first data output control signal KDATAIN1, the NAND gate NA1 and the inverter I3 logically multiply the control signals KDATA and READ2P and generate the second data output control signal KDATAIN2.
The transmission gate 44 transmits the data output control signal pair DBB and DB latched in the register 42 as the data output signal pair DCB and DC responsive to the first data output control signal KDATAIN1. The latch 46 latches the data output control signal pair DCB and DC provided from the transmission gate 44. In other words, the transmission gate 44 and the latch 46, delay the data latched in the register 42 by 1 cycle responsive to the first data output control signal KDATAIN1.
The enable signal generating circuit for enabling the sense amplifier and the data output buffer is similar to the circuit described with reference to FIG. 3b.
FIG. 7a is a timing diagram of the 2 cycles pipelined operation of the data output buffer shown in FIG. 5a where a low frequency clock signal is applied.
In FIG. 7a, the cycle time of the clock signal is approximately 10ns. Of these, it takes 5-6ns (this is almost a fixed amount of time) for the read data to be latched in the latch of the register 42 after the read command is received.
The control signal KDATA is enabled responsive to the clock signal XCK during the execution of the read command. The control signal READ1P is enabled 1 cycle after the read command is received and the control signal READ2P is enabled 2 cycles after the read command is received, as described above. In the timing diagram shown in FIG. 7a, only the read command is continuously inputted. The control signal READ1P is always enabled in the second cycle II. The control signal READ2P is always enabled in the third cycle III. The first data output control signal KDATAIN1 is generated after the control signals KDATA and READ1P are logically multiplied. The control signal KDATAIN1 is synchronized with the control signal KDATA in the third cycle III. The data output buffer is enabled responsive to the controls signals described above.
In the first cycle I, the read data corresponding to the first read command is latched in the register 42 of the data output buffer after 5-6ns (to be used from be as an exemplary predetermined time). In the second cycle II, the read data D1 is latched in the latch 46 through the transmission gate 44 responsive to the first data output control signal. Then, the read data D2 corresponding to the second read command is latched in the register 42 of the data output buffer after lapse of the predetermined time. In the third cycle III, the read data D1 is latched in the latch 50 through the inverter 48 responsive to the second data output control signal KDATAIN2. The read data D1 is then provided to external circuitry through the logical multiplication means 52 responsive to the data output enable signal OE. The read data D2 is latched in the latch 46 through the transmission gate 44 responsive to the first data output control signal KDATAIN1. Then, the read data D3 corresponding to the third read command is latched in the register 42 of the data output buffer.
In the fourth cycle IV, the read data D2 provided to external circuitry responsive to the second data output control signal KDATAIN2. The read data D3 is latched in the latch 46 responsive to the first data output control signal KDATAIN1. The read data D4 corresponding to the fourth read command is latched in the register 42 of the data output buffer. Therefore, the circuit in FIG. 6 can precisely perform the 2 cycles pipelined operation in the continuous read cycle where a low frequency clock signal is applied.
FIG. 7b is a timing diagram of the 2 cycles pipelined operation of the data output buffer shown in FIG. 6 where a high frequency clock signal is applied.
In FIG. 7b, the cycle time of the clock signal is approximately 3ns. Of these, it takes 5-6ns (this is almost a fixed amount of time) for the read data to be latched into the latch of the register 42 after the read command is received.
In the first cycle I, the read data D1 corresponding to the first read command is read. In the second cycle II, the read data D2 corresponding to the second read command is read and the read data D1 is provided to the data output buffer after the predetermined time. In the third cycle III, the read data D3 corresponding to the third read command is read, and the read data D1 is latched in the register 42 of the data output buffer. The read data D2 is provided to the data output buffer. In the fourth cycle, the read data D4 corresponding to the fourth read command is read. The read data D2 is then latched in the register 32 of the data output buffer. The read data D1 is latched in the latch through the transmission gate 44 responsive to the control signal KDATAIN1. The read data D1 is then latched in the latch 50 through the inverter 48 responsive to the second data output control signal KDATAIN2. The read data D1 is outputted to external circuitry as output data Q1 through the logical multiplication means 52 responsive to the data output enable signal OE. The read data D2 is latched in the register 42 of the data output buffer.
If the data output buffer shown in FIG. 6 were functioning properly, it should output the read data D1 in the third cycle III. However, the data output buffer makes the error of outputting the read data D1 in the fourth cycle IV instead. Therefore, it cannot precisely perform the 2 cycles pipelined operation in the continuous read cycle. As described above, the data output buffer shown in FIG. 6 is able to perform the 2 cycles pipelined read operation where a frequency clock signal is applied, but makes errors when a high frequency clock signal is applied.
Accordingly, a need remains for a semiconductor memory device having a data output buffer capable of performing the 2 cycles read operation in both low and high frequencies.